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| data sheet 06.95 advance information mi c r o c omp u ter compone n t s c167cr 1 6 -bit cmos single-chip microcontroller
edition 06.95 published by siemens ag, bereich halbleiter, marketing- kommunikation, balanstra?e 73, 81541 mnchen ? siemens ag 1995. all rights reserved. attention please! as far as patents or other rights of third par- ties are concerned, liability is only assumed for components, not for applications, pro- cesses and circuits implemented within com- ponents or assemblies. the information describes the type of compo- nent and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens companies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for in- formation on the types in question please contact your nearest siemens office, semi- conductor group. siemens ag is an approved cecc manufac- turer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us un- sorted or which we are not obliged to accept, we shall have to invoice you for any costs in- curred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the ex- press written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support de- vice or system, or to affect its safety or ef- fectiveness of that device or system. 2 life support devices or systems are in- tended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be endangered. ausgabe 06.95 herausgegeben von siemens ag, bereich halbleiter, marketing- kommunikation, balanstra?e 73, 81541 mnchen ? siemens ag 1995. alle rechte vorbehalten. wichtige hinweise! gew?hr fr die freiheit von rechten dritter leisten wir nur fr bauelemente selbst, nicht fr anwendungen, verfahren und fr die in bauelementen oder baugruppen realisierten schaltungen. mit den angaben werden die bauelemente spezifiziert, nicht eigenschaften zugesichert. lieferm?glichkeiten und technische ?nderun- gen vorbehalten. fragen ber technik, preise und lieferm?g- lichkeiten richten sie bitte an den ihnen n?chstgelegenen vertrieb halbleiter in deutschland oder an unsere landesgesell- schaften im ausland. bauelemente k?nnen aufgrund technischer erfordernisse gefahrstoffe enthalten. aus- knfte darber bitten wir unter angabe des betreffenden typs ebenfalls ber den vertrieb halbleiter einzuholen. die siemens ag ist ein hersteller von cecc- qualifizierten produkten. verpackung bitte benutzen sie die ihnen bekannten ver- werter. wir helfen ihnen auch weiter C wen- den sie sich an ihren fr sie zust?ndigen ver- trieb halbleiter. nach rcksprache nehmen wir verpackungsmaterial sortiert zurck. die transportkosten mssen sie tragen. fr verpackungsmaterial, das unsortiert an uns zurckgeliefert wird oder fr das wir keine rcknahmepflicht haben, mssen wir ihnen die anfallenden kosten in rechnung stellen. bausteine in lebenserhaltenden ger?ten oder systemen mssen ausdrcklich da- fr zugelassen sein! kritische bauelemente 1 des bereichs halblei- ter der siemens ag drfen nur mit ausdrckli- cher schriftlicher genehmigung des bereichs halbleiter der siemens ag in lebenserhalten- den ger?ten oder systemen 2 eingesetzt wer- den. 1 ein kritisches bauelement ist ein in einem lebenserhaltenden ger?t oder system ein- gesetztes bauelement, bei dessen ausfall berechtigter grund zur annahme besteht, da? das lebenserhaltende ger?t oder sy- stem ausf?llt bzw. dessen sicherheit oder wirksamkeit beeintr?chtigt wird. 2 lebenserhaltende ger?te und systeme sind (a) zur chirurgischen einpflanzung in den menschlichen k?rper gedacht, oder (b) untersttzen bzw. erhalten das menschliche leben. sollten sie ausfallen, besteht berechtigter grund zur annahme, da? die gesundheit des anwenders ge- f?hrdet werden kann. controller area network (can); license of robert bosch gmbh c167cr revision history: original version: 06.95 (advance information) previous releases: data sheet c167 06.94 page subjects (changes compared to c167) 32 register picon added 37 v ils , v ihs , hys, i ov added. 37 r rst , i rwh , i rwl , i alel , i aleh , i p6h , test cond. i ozx changed. 38 i p6l , i cc , i id changed. 39 i cc , i id typical values added 40 adc specification changed. 43...45 pll description added. 45 external clock drive specification changed. 47 t 14 , t 15 , t 16 , t 17 , t 22 , t 39 , t 46 changed. 47 t 47 changed. 53 t 14 , t 15 , t 16 , t 17 , t 20 , t 21, t 22 changed. 54 t 39 , t 46 , t 47 , t 55 changed. 57, 58 t 53 changed to t 68 . 59 t 36 changed. 63 t 63 changed. semiconductor group 1 06.95 l high performance 16-bit cpu with 4-stage pipeline l 100 ns instruction cycle time at 20 mhz cpu clock l 500 ns multiplication (16 16 bit), 1 m s division (32 / 16 bit) l enhanced boolean bit manipulation facilities l additional instructions to support hll and operating systems l register-based design with multiple variable register banks l single-cycle context switching support l clock generation via on-chip pll or via direct clock input l up to 16 mbytes linear address space for code and data l 2 kbytes on-chip internal ram (iram) l 2 kbytes on-chip extension ram (xram) l programmable external bus characteristics for different address ranges l 8-bit or 16-bit external data bus l multiplexed or demultiplexed external address/data buses l five programmable chip-select signals l hold- and hold-acknowledge bus arbitration support l 1024 bytes on-chip special function register area l idle and power down modes l 8-channel interrupt-driven single-cycle data transfer facilities via peripheral event controller (pec) l 16-priority-level interrupt system with 56 sources, sample-rate down to 50 ns l 16-channel 10-bit a/d converter with 9.7 m s conversion time l two 16-channel capture/compare units l 4-channel pwm unit l two multi-functional general purpose timer units with 5 timers l two serial channels (synchronous/asynchronous and high-speed-synchronous) l on-chip can interface with 15 message objects (full-can/basic-can) l programmable watchdog timer l up to 111 general purpose i/o lines, partly with selectable input thresholds and hysteresis l supported by a wealth of development tools like c-compilers, macro-assembler packages, emulators, evaluation boards, hll-debuggers, simulators, logic analyzer disassemblers, programming boards l on-chip bootstrap loader l 144-pin mqfp package (eiaj) this document describes the sab-c167cr-lm , the saf-c167cr-lm and the sak-c167cr-lm . for simplicity all versions are referred to by the term c167cr throughout this document. c16x-family of high-performance cmos 16-bit microcontrollers advance information c167cr 16-bit microcontroller c167cr c167cr semiconductor group 2 controller area network (can); license of robert bosch gmbh c167cr revision history: original version: 06.95 (advance information) previous releases: data sheet c167 06.94 page subjects (changes compared to c167) 32 register picon added 37 v ils , v ihs , hys, i ov added. 37 r rst , i rwh , i rwl , i alel , i aleh , i p6h , test cond. i ozx changed. 38 i p6l , i cc , i id changed. 39 i cc , i id typical values added 40 adc specification changed. 43...45 pll description added. 45 external clock drive specification changed. 47 t 14 , t 15 , t 16 , t 17 , t 22 , t 39 , t 46 changed. 47 t 47 changed. 53 t 14 , t 15 , t 16 , t 17 , t 20 , t 21, t 22 changed. 54 t 39 , t 46 , t 47 , t 55 changed. 57, 58 t 53 changed to t 68 . 59 t 36 changed. 63 t 63 changed. c167cr semiconductor group 3 introduction the c167cr is a new derivative of the siemens c16x family of full featured single-chip cmos microcontrollers. it combines high cpu performance (up to 10 million instructions per second) with high peripheral functionality and enhanced io-capabilities. it also provides on-chip high-speed ram and clock generation via pll. figure 1 logic symbol ordering information type ordering code package function sab-c167cr-lm Q67121-C942 p-mqfp-144-1 16-bit microcontroller with 2 2 kbyte ram temperature range 0 to + 70 c saf-c167cr-lm q67121-c946 p-mqfp-144-1 16-bit microcontroller with 2 2 kbyte ram temperature range - 40 to + 85 c sak-c167cr-lm q67121-c967 p-mqfp-144-1 16-bit microcontroller with 2 2 kbyte ram temperature range - 40 to + 125 c c167cr c167cr semiconductor group 4 pin configuration (top view) figure 2 c167cr a22/can_txd /can_rxd c167cr semiconductor group 5 pin definitions and functions symbol pin number input (i) output (o) function p6.0 - p6.7 1 - 8 1 ... 5 6 7 8 i/o o ... o i o o port 6 is an 8-bit bidirectional i/o port. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high- impedance state. port 6 outputs can be configured as push/ pull or open drain drivers. the following port 6 pins also serve for alternate functions: p6.0 cs0 chip select 0 output ... ... ... p6.4 cs4 chip select 4 output p6.5 hold external master hold request input p6.6 hlda hold acknowledge output p6.7 breq bus request output p8.0 - p8.7 9 - 16 9 ... 16 i/o i/o ... i/o port 8 is an 8-bit bidirectional i/o port. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high- impedance state. port 8 outputs can be configured as push/ pull or open drain drivers. the input threshold of port 8 is selectable (ttl or special). the following port 8 pins also serve for alternate functions: p8.0 cc16io capcom2: cc16 cap.-in/comp.out ... ... ... p8.7 cc23io capcom2: cc23 cap.-in/comp.out p7.0 - p7.7 19 - 26 19 ... 22 23 ... 26 i/o o ... o i/o ... i/o port 7 is an 8-bit bidirectional i/o port. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high- impedance state. port 7 outputs can be configured as push/ pull or open drain drivers. the input threshold of port 7 is selectable (ttl or special). the following port 7 pins also serve for alternate functions: p7.0 pout0 pwm channel 0 output ... ... ... p7.3 pout3 pwm channel 3 output p7.4 cc28io capcom2: cc28 cap.-in/comp.out ... ... ... p7.7 cc31io capcom2: cc31 cap.-in/comp.out c167cr semiconductor group 6 p5.0 - p5.15 27 - 36 39 - 44 39 40 41 42 43 44 i i i i i i i i port 5 is a 16-bit input-only port with schmitt-trigger characteristics. the pins of port 5 also serve as the (up to 16) analog input channels for the a/d converter, where p5.x equals anx (analog input channel x), or they serve as timer inputs: p5.10 t6eud gpt2 timer t6 ext.up/down ctrl.input p5.11 t5eud gpt2 timer t5 ext.up/down ctrl.input p5.12 t6in gpt2 timer t6 count input p5.13 t5in gpt2 timer t5 count input p5.14 t4eud gpt1 timer t4 ext.up/down ctrl.input p5.15 t2eud gpt1 timer t2 ext.up/down ctrl.input p2.0 - p2.15 47 - 54 57 - 64 47 ... 54 57 ... 64 i/o i/o ... i/o i/o i ... i/o i i port 2 is a 16-bit bidirectional i/o port. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high- impedance state. port 2 outputs can be configured as push/ pull or open drain drivers. the input threshold of port 2 is selectable (ttl or special). the following port 2 pins also serve for alternate functions: p2.0 cc0io capcom: cc0 cap.-in/comp.out ... ... ... p2.7 cc7io capcom: cc7 cap.-in/comp.out p2.8 cc8io capcom: cc8 cap.-in/comp.out, ex0in fast external interrupt 0 input ... ... ... p2.15 cc15io capcom: cc15 cap.-in/comp.out, ex7in fast external interrupt 7 input t7in capcom2 timer t7 count input pin definitions and functions (cont?) symbol pin number input (i) output (o) function c167cr semiconductor group 7 p3.0 - p3.13, p3.15 65 - 70, 73 - 80, 81 65 66 67 68 69 70 73 74 75 76 77 78 79 80 81 i/o i/o i/o i o i o i i i i i/o i/o o i/o o o i/o o port 3 is a 15-bit (p3.14 is missing) bidirectional i/o port. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high- impedance state. port 3 outputs can be configured as push/ pull or open drain drivers. the input threshold of port 3 is selectable (ttl or special). the following port 3 pins also serve for alternate functions: p3.0 t0in capcom timer t0 count input p3.1 t6out gpt2 timer t6 toggle latch output p3.2 capin gpt2 register caprel capture input p3.3 t3out gpt1 timer t3 toggle latch output p3.4 t3eud gpt1 timer t3 ext.up/down ctrl.input p3.5 t4in gpt1 timer t4 input for count/gate/reload/capture p3.6 t3in gpt1 timer t3 count/gate input p3.7 t2in gpt1 timer t2 input for count/gate/reload/capture p3.8 mrst ssc master-rec./slave-transmit i/o p3.9 mtsr ssc master-transmit/slave-rec. o/i p3.10 t d0 asc0 clock/data output (asyn./syn.) p3.11 r d0 asc0 data input (asyn.) or i/o (syn.) p3.12 bhe ext. memory high byte enable signal, wrh ext. memory high byte write strobe p3.13 sclk ssc master clock outp./slave cl. inp. p3.15 clkout system clock output (=cpu clock) p4.0 - p4.7 85 - 92 85 ... 89 90 91 92 i/o o ... o o i o o o port 4 is an 8-bit bidirectional i/o port. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high- impedance state. in case of an external bus configuration, port 4 can be used to output the segment address lines: p4.0 least significant segment addr. line ... ... ... p4.4 a16 least significant segment addr. line p4.5 a21 segment address line, can_rxd can receive data input p4.6 a22 segment address line, can_txd can transmit data output p4.7 a23 most significant segment addr. line rd 95 o external memory read strobe. rd is activated for every external instruction or data read access. pin definitions and functions (cont?) symbol pin number input (i) output (o) function c167cr semiconductor group 8 wr / wrl 96 o external memory write strobe. in wr -mode this pin is activated for every external data write access. in wrl -mode this pin is activated for low byte data write accesses on a 16- bit bus, and for every data write access on an 8-bit bus. see wrcfg in register syscon for mode selection. ready 97 i ready input. when the ready function is enabled, a high level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. ale 98 o address latch enable output. can be used for latching the address into external memory or an address latch in the multiplexed bus modes. ea 99 i external access enable pin. a low level at this pin during and after reset forces the c167cr to begin instruction execution out of external memory. a high level forces execution out of the internal rom. romless versions must have this pin tied to ?? port0: p0l.0 - p0l.7, p0h.0 - p0h.7 100 - 107 108, 111-117 i/o port0 consists of the two 8-bit bidirectional i/o ports p0l and p0h. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high-impedance state. in case of an external bus configuration, port0 serves as the address (a) and address/data (ad) bus in multiplexed bus modes and as the data (d) bus in demultiplexed bus modes. demultiplexed bus modes: data path width: 8-bit 16-bit p0l.0 - p0l.7: d0 - d7 d0 - d7 p0h.0 - p0h.7: i/o d8 - d15 multiplexed bus modes: data path width: 8-bit 16-bit p0l.0 - p0l.7: ad0 - ad7 ad0 - ad7 p0h.0 - p0h.7: a8 - a15 ad8 - ad15 pin definitions and functions (cont?) symbol pin number input (i) output (o) function c167cr semiconductor group 9 port1: p1l.0 - p1l.7, p1h.0 - p1h.7 118 - 125 128 - 135 132 133 134 135 i/o i i i i port1 consists of the two 8-bit bidirectional i/o ports p1l and p1h. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high-impedance state. port1 is used as the 16-bit address bus (a) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. the following port1 pins also serve for alternate functions: p1h.4 cc24io capcom2: cc24 capture input p1h.5 cc25io capcom2: cc25 capture input p1h.6 cc26io capcom2: cc26 capture input p1h.7 cc27io capcom2: cc27 capture input xtal1 xtal2 138 137 i o xtal1: input to the oscillator amplifier and input to the internal clock generator xtal2: output of the oscillator amplifier circuit. to clock the device from an external source, drive xtal1, while leaving xtal2 unconnected. minimum and maximum high/low and rise/fall times specified in the ac characteristics must be observed. rstin 140 i reset input with schmitt-trigger characteristics. a low level at this pin for a specified duration while the oscillator is running resets the c167cr. an internal pullup resistor permits power- on reset using only a capacitor connected to v ss . rstout 141 o internal reset indication output. this pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. rstout remains low until the einit (end of initialization) instruction is executed. nmi 142 i non-maskable interrupt input. a high to low transition at this pin causes the cpu to vector to the nmi trap routine. when the pwrdn (power down) instruction is executed, the nmi pin must be low in order to force the c167cr to go into power down mode. if nmi is high, when pwrdn is executed, the part will continue to run in normal mode. if not used, pin nmi should be pulled high externally. v aref 37 ? reference voltage for the a/d converter. v agnd 38 ? reference ground for the a/d converter. v pp 84 ? flash programming voltage. this pin accepts the programming voltage for flash versions of the c167cr. note: this pin is not connected ( nc ) on non-flash versions. pin definitions and functions (cont?) symbol pin number input (i) output (o) function c167cr semiconductor group 10 v cc 17, 46, 56, 72, 82, 93, 109, 126, 136, 144 ? digital supply voltage: + 5 v during normal operation and idle mode. 3 2.5 v during power down mode. v ss 18, 45, 55, 71, 83, 94, 110, 127, 139, 143 ?digital ground. pin definitions and functions (cont?) symbol pin number input (i) output (o) function c167cr semiconductor group 11 functional description the architecture of the c167cr combines advantages of both risc and cisc processors and of advanced peripheral subsystems in a very well-balanced way. the following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the c167cr. note : all time specifications refer to a cpu clock of 20 mhz (see definition in the ac characteristics section). figure 3 block diagram c167cr semiconductor group 12 memory organization the memory space of the c167cr is configured in a von neumann architecture which means that code memory, data memory, registers and i/o ports are organized within the same linear address space which includes 16 mbytes. the entire memory space can be accessed bytewise or wordwise. particular portions of the on-chip memory have additionally been made directly bitaddressable. the c167cr is prepared to incorporate on-chip mask-programmable rom or flash memory for code or constant data. currently no rom is integrated. 2 kbytes of on-chip internal ram are provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. a register bank can consist of up to 16 wordwide (r0 to r15) and/or bytewide (rl0, rh0, ? rl7, rh7) so-called general purpose registers (gprs). 1024 bytes (2 512 bytes) of the address space are reserved for the special function register areas (sfr space and esfr space). sfrs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. unused sfr addresses are reserved for future members of the c16x family. 2 kbytes of on-chip extension ram (xram) are provided to store user data, user stacks or code. the xram is accessed like external memory and therefore cannot be used for the system stack or for register banks and is not bitadressable. the xram allows 16-bit accesses with maximum speed. in order to meet the needs of designs where more memory is required than is provided on chip, up to 16 mbytes of external ram and/or rom can be connected to the microcontroller. external bus controller all of the external memory accesses are performed by a particular on-chip external bus controller (ebc). it can be programmed either to single chip mode when no external memory is required, or to one of four different external memory access modes, which are as follows: 16-/18-/20-/24-bit addresses, 16-bit data, demultiplexed 16-/18-/20-/24-bit addresses, 16-bit data, multiplexed 16-/18-/20-/24-bit addresses, 8-bit data, multiplexed 16-/18-/20-/24-bit addresses, 8-bit data, demultiplexed in the demultiplexed bus modes, addresses are output on port1 and data is input/output on port0. in the multiplexed bus modes both addresses and data use port0 for input/output. important timing characteristics of the external bus interface (memory cycle time, memory tri- state time, length of ale and read write delay) have been made programmable to allow the user the adaption of a wide range of different types of memories. in addition, different address ranges may be accessed with different bus characteristics. up to 5 external cs signals can be generated in order to save external glue logic. access to very slow memories is supported via a particular ?eady?function. a hold /hlda protocol is available for bus arbitration. for applications which require less than 16 mbytes of external memory space, this address space can be restricted to 1 mbyte, 256 kbyte or to 64 kbyte. in this case port 4 outputs four, two or no address lines at all. it outputs all 8 address lines, if an address space of 16 mbytes is used. c167cr semiconductor group 13 central processing unit (cpu) the main core of the cpu consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (alu) and dedicated sfrs. additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. based on these hardware provisions, most of the c167cr? instructions can be executed in just one machine cycle which requires 100 ns at 20-mhz cpu clock. for example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. all multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. another pipeline optimization, the so-called ?ump cache? allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle. figure 4 cpu block diagram c167cr semiconductor group 14 the cpu disposes of an actual register context consisting of up to 16 wordwide gprs which are physically allocated within the on-chip ram area. a context pointer (cp) register determines the base address of the active register bank to be accessed by the cpu at a time. the number of register banks is only restricted by the available internal ram space. for easy parameter passing, a register bank may overlap others. a system stack of up to 2048 bytes is provided as a storage for temporary data. the system stack is allocated in the on-chip ram area, and it is accessed by the cpu via the stack pointer (sp) register. two separate sfrs, stkov and stkun, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. the high performance offered by the hardware implementation of the cpu can efficiently be utilized by a programmer via the highly efficient c167cr instruction set which includes the following instruction classes: arithmetic instructions logical instructions boolean bit manipulation instructions compare and loop control instructions shift and rotate instructions prioritize instruction data movement instructions system stack instructions jump and call instructions return instructions system control instructions miscellaneous instructions the basic instruction length is either 2 or 4 bytes. possible operand types are bits, bytes and words. a variety of direct, indirect or immediate addressing modes are provided to specify the required operands. c167cr semiconductor group 15 interrupt system with an interrupt response time within a range from just 250 ns to 600 ns (in case of internal program execution), the c167cr is capable of reacting very fast to the occurrence of non- deterministic events. the architecture of the c167cr supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. any of these interrupt requests can be programmed to being serviced by the interrupt controller or by the peripheral event controller (pec). in contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ?tolen?from the current cpu activity to perform a pec service. a pec service implies a single byte or word data transfer between any two memory locations with an additional increment of either the pec source or the destination pointer. an individual pec transfer counter is implicity decremented for each pec service except when performing in the continuous transfer mode. when this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. pec services are very well suited, for example, for supporting the transmission or reception of blocks of data. the c167cr has 8 pec channels each of which offers such fast interrupt-driven data transfer capabilities. a separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. via its related register, each source can be programmed to one of sixteen interrupt priority levels. once having been accepted by the cpu, an interrupt service can only be interrupted by a higher prioritized service request. for the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. fast external interrupt inputs are provided to service external interrupts with high precision requirements. these fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). software interrupts are supported by means of the ?rap?instruction in combination with an individual trap (interrupt) number. the following table shows all of the possible c167cr interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: note: three nodes in the table (x-peripheral nodes) are prepared to accept interrupt requests from integrated x-bus peripherals. nodes, where no x-peripherals are connected, may be used to generate software controlled interrupt requests by setting the respective xpnir bit. c167cr semiconductor group 16 source of interrupt or pec service request request flag enable flag interrupt vector vector location trap number capcom register 0 cc0ir cc0ie cc0int 00?040 h 10 h capcom register 1 cc1ir cc1ie cc1int 00?044 h 11 h capcom register 2 cc2ir cc2ie cc2int 00?048 h 12 h capcom register 3 cc3ir cc3ie cc3int 00?04c h 13 h capcom register 4 cc4ir cc4ie cc4int 00?050 h 14 h capcom register 5 cc5ir cc5ie cc5int 00?054 h 15 h capcom register 6 cc6ir cc6ie cc6int 00?058 h 16 h capcom register 7 cc7ir cc7ie cc7int 00?05c h 17 h capcom register 8 cc8ir cc8ie cc8int 00?060 h 18 h capcom register 9 cc9ir cc9ie cc9int 00?064 h 19 h capcom register 10 cc10ir cc10ie cc10int 00?068 h 1a h capcom register 11 cc11ir cc11ie cc11int 00?06c h 1b h capcom register 12 cc12ir cc12ie cc12int 00?070 h 1c h capcom register 13 cc13ir cc13ie cc13int 00?074 h 1d h capcom register 14 cc14ir cc14ie cc14int 00?078 h 1e h capcom register 15 cc15ir cc15ie cc15int 00?07c h 1f h capcom register 16 cc16ir cc16ie cc16int 00?0c0 h 30 h capcom register 17 cc17ir cc17ie cc17int 00?0c4 h 31 h capcom register 18 cc18ir cc18ie cc18int 00?0c8 h 32 h capcom register 19 cc19ir cc19ie cc19int 00?0cc h 33 h capcom register 20 cc20ir cc20ie cc20int 00?0d0 h 34 h capcom register 21 cc21ir cc21ie cc21int 00?0d4 h 35 h capcom register 22 cc22ir cc22ie cc22int 00?0d8 h 36 h capcom register 23 cc23ir cc23ie cc23int 00?0dc h 37 h capcom register 24 cc24ir cc24ie cc24int 00?0e0 h 38 h capcom register 25 cc25ir cc25ie cc25int 00?0e4 h 39 h capcom register 26 cc26ir cc26ie cc26int 00?0e8 h 3a h capcom register 27 cc27ir cc27ie cc27int 00?0ec h 3b h capcom register 28 cc28ir cc28ie cc28int 00?0e0 h 3c h capcom register 29 cc29ir cc29ie cc29int 00?110 h 44 h capcom register 30 cc30ir cc30ie cc30int 00?114 h 45 h capcom register 31 cc31ir cc31ie cc31int 00?118 h 46 h capcom timer 0 t0ir t0ie t0int 00?080 h 20 h c167cr semiconductor group 17 capcom timer 1 t1ir t1ie t1int 00?084 h 21 h capcom timer 7 t7ir t7ie t7int 00?0f4 h 3d h capcom timer 8 t8ir t8ie t8int 00?0f8 h 3e h gpt1 timer 2 t2ir t2ie t2int 00?088 h 22 h gpt1 timer 3 t3ir t3ie t3int 00?08c h 23 h gpt1 timer 4 t4ir t4ie t4int 00?090 h 24 h gpt2 timer 5 t5ir t5ie t5int 00?094 h 25 h gpt2 timer 6 t6ir t6ie t6int 00?098 h 26 h gpt2 caprel register crir crie crint 00?09c h 27 h a/d conversion complete adcir adcie adcint 00?0a0 h 28 h a/d overrun error adeir adeie adeint 00?0a4 h 29 h asc0 transmit s0tir s0tie s0tint 00?0a8 h 2a h asc0 transmit buffer s0tbir s0tbie s0tbint 00?11c h 47 h asc0 receive s0rir s0rie s0rint 00?0ac h 2b h asc0 error s0eir s0eie s0eint 00?0b0 h 2c h ssc transmit sctir sctie sctint 00?0b4 h 2d h ssc receive scrir scrie scrint 00?0b8 h 2e h ssc error sceir sceie sceint 00?0bc h 2f h pwm channel 0...3 pwmir pwmie pwmint 00?0fc h 3f h can interface xp0ir xp0ie xp0int 00?100 h 40 h x-peripheral node xp1ir xp1ie xp1int 00?104 h 41 h x-peripheral node xp2ir xp2ie xp2int 00?108 h 42 h pll unlock xp3ir xp3ie xp3int 00?10c h 43 h source of interrupt or pec service request request flag enable flag interrupt vector vector location trap number c167cr semiconductor group 18 the c167cr also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ?ardware traps? hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). the occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (tfr). except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. in turn, hardware trap services can normally not be interrupted by standard or pec interrupts. the following table shows all of the possible exceptions or error conditions that can arise during run- time: exception condition trap flag trap vector vector location trap number trap priority reset functions: hardware reset software reset watchdog timer overflow reset reset reset 00?000 h 00?000 h 00?000 h 00 h 00 h 00 h iii iii iii class a hardware traps: non-maskable interrupt stack overflow stack underflow nmi stkof stkuf nmitrap stotrap stutrap 00?008 h 00?010 h 00?018 h 02 h 04 h 06 h ii ii ii class b hardware traps: undefined opcode protected instruction fault illegal word operand access illegal instruction access illegal external bus access undopc prtflt illopa illina illbus btrap btrap btrap btrap btrap 00?028 h 00?028 h 00?028 h 00?028 h 00?028 h 0a h 0a h 0a h 0a h 0a h i i i i i reserved [2c h ?3c h ] [0b h ?0f h ] software traps trap instruction any [00?000 h ? 00?1fc h ] in steps of 4 h any [00 h ?7f h ] current cpu priority c167cr semiconductor group 19 capture/compare (capcom) units the capcom units support generation and control of timing sequences on up to 32 channels with a maximum resolution of 400 ns (at 20-mhz system clock). the capcom units are typically used to handle high speed i/o tasks such as pulse and waveform generation, pulse width modulation (pmw), digital to analog (d/a) conversion, software timing, or time recording relative to external events. four 16-bit timers (t0/t1, t7/t8) with reload registers provide two independent time bases for the capture/compare register array. the input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer t6 in module gpt2. this provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements. in addition, external count inputs for capcom timers t0 and t7 allow event scheduling for the capture/compare registers relative to external events. both of the two capture/compare register arrays contain 16 dual purpose capture/compare registers, each of which may be individually allocated to either capcom timer t0 or t1 (t7 or t8, respectively), and programmed for capture or compare function. each register has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin (except for cc24...cc27) to indicate the occurrence of a compare event. when a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (?apture?) into the capture/compare register in response to an external event at the port pin which is associated with this register. in addition, a specific interrupt request for this capture/compare register is generated. either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. the contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. when a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode. compare modes function mode 0 interrupt-only compare mode; several compare interrupts per timer period are possible mode 1 pin toggles on each compare match; several compare events per timer period are possible mode 2 interrupt-only compare mode; only one compare interrupt per timer period is generated mode 3 pin set ??on match; pin reset ??on compare time overflow; only one compare event per timer period is generated double register mode two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible. c167cr semiconductor group 20 figure 5 capcom unit block diagram *) *) 12 outputs on capcom2 c167cr semiconductor group 21 pwm module the pulse width modulation module can generate up to four pwm output signals using edge- aligned or center-aligned pwm. in addition the pwm module can generate pwm burst signals and single shot outputs. the frequency range of the pwm signals covers 4.8 hz to 1 mhz (referred to a cpu clock of 20 mhz), depending on the resolution of the pwm output signal. the level of the output signals is selectable and the pwm module can generate interrupt requests. general purpose timer (gpt) unit the gpt unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. the gpt unit incorporates five 16-bit timers which are organized in two separate modules, gpt1 and gpt2. each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. each of the three timers t2, t3, t4 of module gpt1 can be configured individually for one of three basic modes of operation, which are timer, gated timer, and counter mode. in timer mode, the input clock for a timer is derived from the cpu clock, divided by a programmable prescaler, while counter mode allows a timer to be clocked in reference to external events. pulse width or duty cycle measurement is supported in gated timer mode, where the operation of a timer is controlled by the ?ate?level on an external input pin. for these purposes, each timer has one associated port pin (txin) which serves as gate or clock input. the maximum resolution of the timers in module gpt1 is 400 ns (@ 20-mhz cpu clock). the count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (txeud) to facilitate e. g. position tracking. timers t3 and t4 have output toggle latches (txotl) which change their state on each timer over- flow/underflow. the state of these latches may be output on port pins (txout) e. g. for time out monitoring of external hardware components, or may be used internally to clock timers t2 and t4 for measuring long time periods with high resolution. in addition to their basic operating modes, timers t2 and t4 may be configured as reload or capture registers for timer t3. when used as capture or reload registers, timers t2 and t4 are stopped. the contents of timer t3 is captured into t2 or t4 in response to a signal at their associated input pins (txin). timer t3 is reloaded with the contents of t2 or t4 triggered either by an external signal or by a selectable state transition of its toggle latch t3otl. when both t2 and t4 are configured to alternately reload t3 on opposite state transitions of t3otl with the low and high times of a pwm signal, this signal can be constantly generated without software intervention. with its maximum resolution of 200 ns (@ 20 mhz), the gpt2 module provides precise event control and time measurement. it includes two timers (t5, t6) and a capture/reload register (caprel). both timers can be clocked with an input clock which is derived from the cpu clock via a programmable prescaler or with external signals. the count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (txeud). concatenation of the timers is supported via the output toggle latch (t6otl) of timer t6, which changes its state on each timer overflow/underflow. c167cr semiconductor group 22 the state of this latch may be used to clock timer t5, or it may be output on a port pin (t6out). the overflows/underflows of timer t6 can additionally be used to clock the capcom timers t0 or t1, and to cause a reload from the caprel register. the caprel register may capture the contents of timer t5 based on an external signal transition on the corresponding port pin (capin), and timer t5 may optionally be cleared after the capture procedure. this allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. figure 6 block diagram of gpt1 c167cr semiconductor group 23 figure 7 block diagram of gpt2 watchdog timer the watchdog timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. the watchdog timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the einit (end of initialization) instruction has been executed. thus, the chip? start-up procedure is always monitored. the software has to be designed to service the watchdog timer before it overflows. if, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates an internal hardware reset and pulls the rstout pin low in order to allow external hardware components to be reset. the watchdog timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128. the high byte of the watchdog timer register can be set to a prespecified reload value (stored in wdtrel) in order to allow further variation of the monitored time interval. each time it is serviced by the application software, the high byte of the watchdog timer is reloaded. thus, time intervals between 25 m s and 420 ms can be monitored (@ 20 mhz). the default watchdog timer interval after reset is 6.55 ms (@ 20 mhz). c167cr semiconductor group 24 a/d converter for analog signal measurement, a 10-bit a/d converter with 16 multiplexed input channels and a sample and hold circuit has been integrated on-chip. it uses the method of successive approximation. the sample time (for loading the capacitors) and the conversion time is programmable and can so be adjusted to the external circuitry. overrun error detection/protection is provided for the conversion result register (addat): either an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended in such a case until the previous result has been read. for applications which require less than 16 analog input channels, the remaining channel inputs can be used as digital input port pins. the a/d converter of the c167cr supports four different conversion modes. in the standard single channel conversion mode, the analog level on a specified channel is sampled once and converted to a digital result. in the single channel continuous mode, the analog level on a specified channel is repeatedly sampled and converted without software intervention. in the auto scan mode, the analog levels on a prespecified number of channels are sequentially sampled and converted. in the auto scan continuous mode, the number of prespecified channels is repeatedly sampled and converted. in addition, the conversion of a specific channel can be inserted (injected) into a running sequence without disturbing this sequence. this is called channel injection mode. the peripheral event controller (pec) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. after each reset and also during normal operation the adc automatically performs calibration cycles. this automatic self-calibration constantly adjusts the converter to changing operating conditions (e.g. temperature) and compensates process variations. these calibration cycles are part of the conversion cycle, so they do not affect the normal operation of the a/d converter. c167cr semiconductor group 25 serial channels serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an asynchronous/ synchronous serial channel (asc0) and a high-speed synchronous serial channel (ssc). asc0 is upward compatible with the serial ports of the siemens sab 8051x microcontroller family and support full-duplex asynchronous communication up to 625 kbaud and half-duplex synchronous communication up to 2.5 mbaud on the @ 20-mhz system clock. the ssc allows half duplex synchronous communication up to 5 mbaud @ 20-mhz system clock. two dedicated baud rate generators allow to set up all standard baud rates without oscillator tuning. for transmission, reception, and erroneous reception 3 separate interrupt vectors are provided for each serial channel. in asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. for multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data + wake up bit mode). in synchronous mode, the asc0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the asc0. the ssc transmits or receives characters of 2...16 bits length synchronously to a shift clock which can be generated by the ssc (master mode) or by an external master (slave mode). the ssc can start shifting with the lsb or with the msb, while the asc0 always shifts the lsb first. a loop back option is available for testing purposes. a number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. a parity bit can automatically be generated on transmission or be checked on reception. framing error detection allows to recognize data frames with missing stop bits. an overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. can-module the integrated can-module handles the completely autonomous transmission and reception of can frames in accordance with the can specification v2.0 part b (active), i.e. the on-chip can- module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. the module provides full can functionality on up to 15 message objects. message object 15 may be configured for basic can functionality. both modes provide separate masks for acceptance filtering which allows to accept a number of identifiers in full can mode and also allows to disregard a number of identifiers in basic can mode. all message objects can be updated independent from the other objects and are equipped for the maximum message length of 8 bytes. the bit timing is derived from the xclk and is programmable up to a data rate of 1 mbaud. the can-module uses two pins to interface to a bus transceiver. c167cr semiconductor group 26 parallel ports the c167cr provides up to 111 i/o lines which are organized into eight input/output ports and one input port. all port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. the i/o ports are true bidirectional ports which are switched to high impedance state when configured as inputs. the output drivers of five i/o ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. during the internal reset, all port pins are configured as inputs. the input threshold of port 2, port 3, port 7 and port 8 is selectable (ttl or cmos like), where the special cmos like input threshold reduces noise sensitivity due to the input hysteresis. the input threshold may be selected individually for each byte of the respective ports. all port lines have programmable alternate input or output functions associated with them. port0 and port1 may be used as address and data lines when accessing external memory, while port 4 outputs the additional segment address bits a23/19/17...a16 in systems where segmentation is enabled to access more than 64 kbytes of memory. port 2, port 8 and port 7 are associated with the capture inputs or compare outputs of the capcom units and/or with the outputs of the pwm module. port 6 provides optional bus arbitration signals (breq , hlda , hold ) and chip select signals. port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal bhe and the system clock output (clkout). port 5 is used for the analog input channels to the a/d converter or timer control signals. all port lines that are not used for these alternate functions may be used as general purpose io lines. c167cr semiconductor group 27 instruction set summary the table below lists the instructions of the c167cr in a condensed way. the various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the ?16x family instruction set manual . this document also provides a detailed description of each instruction. instruction set summary mnemonic description bytes add(b) add word (byte) operands 2 / 4 addc(b) add word (byte) operands with carry 2 / 4 sub(b) subtract word (byte) operands 2 / 4 subc(b) subtract word (byte) operands with carry 2 / 4 mul(u) (un)signed multiply direct gpr by direct gpr (16-16-bit) 2 div(u) (un)signed divide register mdl by direct gpr (16-/16-bit) 2 divl(u) (un)signed long divide reg. md by direct gpr (32-/16-bit) 2 cpl(b) complement direct word (byte) gpr 2 neg(b) negate direct word (byte) gpr 2 and(b) bitwise and, (word/byte operands) 2 / 4 or(b) bitwise or, (word/byte operands) 2 / 4 xor(b) bitwise xor, (word/byte operands) 2 / 4 bclr clear direct bit 2 bset set direct bit 2 bmov(n) move (negated) direct bit to direct bit 4 band, bor, bxor and/or/xor direct bit with direct bit 4 bcmp compare direct bit to direct bit 4 bfldh/l bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data 4 cmp(b) compare word (byte) operands 2 / 4 cmpd1/2 compare word data to gpr and decrement gpr by 1/2 2 / 4 cmpi1/2 compare word data to gpr and increment gpr by 1/2 2 / 4 prior determine number of shift cycles to normalize direct word gpr and store result in direct word gpr 2 shl / shr shift left/right direct word gpr 2 rol / ror rotate left/right direct word gpr 2 ashr arithmetic (sign bit) shift right direct word gpr 2 c167cr semiconductor group 28 mov(b) move word (byte) data 2 / 4 movbs move byte operand to word operand with sign extension 2 / 4 movbz move byte operand to word operand. with zero extension 2 / 4 jmpa, jmpi, jmpr jump absolute/indirect/relative if condition is met 4 jmps jump absolute to a code segment 4 j(n)b jump relative if direct bit is (not) set 4 jbc jump relative and clear bit if direct bit is set 4 jnbs jump relative and set bit if direct bit is not set 4 calla, calli, callr call absolute/indirect/relative subroutine if condition is met 4 calls call absolute subroutine in any code segment 4 pcall push direct word register onto system stack and call absolute subroutine 4 trap call interrupt service routine via immediate trap number 2 push, pop push/pop direct word register onto/from system stack 2 scxt push direct word register onto system stack and update register with word operand 4 ret return from intra-segment subroutine 2 rets return from inter-segment subroutine 2 retp return from intra-segment subroutine and pop direct word register from system stack 2 reti return from interrupt service subroutine 2 srst software reset 4 idle enter idle mode 4 pwrdn enter power down mode (supposes nmi -pin being low) 4 srvwdt service watchdog timer 4 diswdt disable watchdog timer 4 einit signify end-of-initialization on rstout-pin 4 atomic begin atomic sequence 2 extr begin extended register sequence 2 extp(r) begin extended page (and register) sequence 2 / 4 exts(r) begin extended segment (and register) sequence 2 / 4 nop null operation 2 instruction set summary (cont?) mnemonic description bytes c167cr semiconductor group 29 special function registers overview the following table lists all sfrs which are implemented in the c167cr in alphabetical order. bit-addressable sfrs are marked with the letter b ?in column ?ame? sfrs within the extended sfr-space (esfrs) are marked with the letter e ?in column ?hysical address? an sfr can be specified via its individual mnemonic name. depending on the selected addressing mode, an sfr can be accessed via its physical address (using the data page pointers), or via its short 8-bit address (without using the data page pointers). special function registers overview name physical address 8-bit address description reset value adcic b ff98 h cc h a/d converter end of conversion interrupt control register 0000 h adcon b ffa0 h d0 h a/d converter control register 0000 h addat fea0 h 50 h a/d converter result register 0000 h addat2 f0a0 h e 50 h a/d converter 2 result register 0000 h addrsel1 fe18 h 0c h address select register 1 0000 h addrsel2 fe1a h 0d h address select register 2 0000 h addrsel3 fe1c h 0e h address select register 3 0000 h addrsel4 fe1e h 0f h address select register 4 0000 h adeic b ff9a h cd h a/d converter overrun error interrupt control register 0000 h buscon0 b ff0c h 86 h bus configuration register 0 0xx0 h buscon1 b ff14 h 8a h bus configuration register 1 0000 h buscon2 b ff16 h 8b h bus configuration register 2 0000 h buscon3 b ff18 h 8c h bus configuration register 3 0000 h buscon4 b ff1a h 8d h bus configuration register 4 0000 h caprel fe4a h 25 h gpt2 capture/reload register 0000 h cc0 fe80 h 40 h capcom register 0 0000 h cc0ic b ff78 h bc h capcom register 0 interrupt control register 0000 h cc1 fe82 h 41 h capcom register 1 0000 h cc1ic b ff7a h bd h capcom register 1 interrupt control register 0000 h cc2 fe84 h 42 h capcom register 2 0000 h cc2ic b ff7c h be h capcom register 2 interrupt control register 0000 h c167cr semiconductor group 30 cc3 fe86 h 43 h capcom register 3 0000 h cc3ic b ff7e h bf h capcom register 3 interrupt control register 0000 h cc4 fe88 h 44 h capcom register 4 0000 h cc4ic b ff80 h c0 h capcom register 4 interrupt control register 0000 h cc5 fe8a h 45 h capcom register 5 0000 h cc5ic b ff82 h c1 h capcom register 5 interrupt control register 0000 h cc6 fe8c h 46 h capcom register 6 0000 h cc6ic b ff84 h c2 h capcom register 6 interrupt control register 0000 h cc7 fe8e h 47 h capcom register 7 0000 h cc7ic b ff86 h c3 h capcom register 7 interrupt control register 0000 h cc8 fe90 h 48 h capcom register 8 0000 h cc8ic b ff88 h c4 h capcom register 8 interrupt control register 0000 h cc9 fe92 h 49 h capcom register 9 0000 h cc9ic b ff8a h c5 h capcom register 9 interrupt control register 0000 h cc10 fe94 h 4a h capcom register 10 0000 h cc10ic b ff8c h c6 h capcom register 10 interrupt control register 0000 h cc11 fe96 h 4b h capcom register 11 0000 h cc11ic b ff8e h c7 h capcom register 11 interrupt control register 0000 h cc12 fe98 h 4c h capcom register 12 0000 h cc12ic b ff90 h c8 h capcom register 12 interrupt control register 0000 h cc13 fe9a h 4d h capcom register 13 0000 h cc13ic b ff92 h c9 h capcom register 13 interrupt control register 0000 h cc14 fe9c h 4e h capcom register 14 0000 h cc14ic b ff94 h ca h capcom register 14 interrupt control register 0000 h cc15 fe9e h 4f h capcom register 15 0000 h cc15ic b ff96 h cb h capcom register 15 interrupt control register 0000 h cc16 fe60 h 30 h capcom register 16 0000 h cc16ic b f160 h e b0 h capcom register 16 interrupt control register 0000 h cc17 fe62 h 31 h capcom register 17 0000 h special function registers overview (cont d) name physical address 8-bit address description reset value c167cr semiconductor group 31 cc17ic b f162 h e b1 h capcom register 17 interrupt control register 0000 h cc18 fe64 h 32 h capcom register 18 0000 h cc18ic b f164 h e b2 h capcom register 18 interrupt control register 0000 h cc19 fe66 h 33 h capcom register 19 0000 h cc19ic b f166 h e b3 h capcom register 19 interrupt control register 0000 h cc20 fe68 h 34 h capcom register 20 0000 h cc20ic b f168 h e b4 h capcom register 20 interrupt control register 0000 h cc21 fe6a h 35 h capcom register 21 0000 h cc21ic b f16a h e b5 h capcom register 21 interrupt control register 0000 h cc22 fe6c h 36 h capcom register 22 0000 h cc22ic b f16c h e b6 h capcom register 22 interrupt control register 0000 h cc23 fe6e h 37 h capcom register 23 0000 h cc23ic b f16e h e b7 h capcom register 23 interrupt control register 0000 h cc24 fe70 h 38 h capcom register 24 0000 h cc24ic b f170 h e b8 h capcom register 24 interrupt control register 0000 h cc25 fe72 h 39 h capcom register 25 0000 h cc25ic b f172 h e b9 h capcom register 25 interrupt control register 0000 h cc26 fe74 h 3a h capcom register 26 0000 h cc26ic b f174 h e ba h capcom register 26 interrupt control register 0000 h cc27 fe76 h 3b h capcom register 27 0000 h cc27ic b f176 h e bb h capcom register 27 interrupt control register 0000 h cc28 fe78 h 3c h capcom register 28 0000 h cc28ic b f178 h e bc h capcom register 28 interrupt control register 0000 h cc29 fe7a h 3d h capcom register 29 0000 h cc29ic b f184 h e c2 h capcom register 29 interrupt control register 0000 h cc30 fe7c h 3e h capcom register 30 0000 h cc30ic b f18c h e c6 h capcom register 30 interrupt control register 0000 h cc31 fe7e h 3f h capcom register 31 0000 h cc31ic b f194 h e ca h capcom register 31 interrupt control register 0000 h special function registers overview (cont d) name physical address 8-bit address description reset value c167cr semiconductor group 32 ccm0 b ff52 h a9 h capcom mode control register 0 0000 h ccm1 b ff54 h aa h capcom mode control register 1 0000 h ccm2 b ff56 h ab h capcom mode control register 2 0000 h ccm3 b ff58 h ac h capcom mode control register 3 0000 h ccm4 b ff22 h 91 h capcom mode control register 4 0000 h ccm5 b ff24 h 92 h capcom mode control register 5 0000 h ccm6 b ff26 h 93 h capcom mode control register 6 0000 h ccm7 b ff28 h 94 h capcom mode control register 7 0000 h cp fe10 h 08 h cpu context pointer register fc00 h cric b ff6a h b5 h gpt2 caprel interrupt control register 0000 h csp fe08 h 04 h cpu code segment pointer register (read only) 0000 h dp0l b f100 h e 80 h p0l direction control register 00 h dp0h b f102 h e 81 h p0h direction control register 00 h dp1l b f104 h e 82 h p1l direction control register 00 h dp1h b f106 h e 83 h p1h direction control register 00 h dp2 b ffc2 h e1 h port 2 direction control register 0000 h dp3 b ffc6 h e3 h port 3 direction control register 0000 h dp4 b ffca h e5 h port 4 direction control register 00 h dp6 b ffce h e7 h port 6 direction control register 00 h dp7 b ffd2 h e9 h port 7 direction control register 00 h dp8 b ffd6 h eb h port 8 direction control register 00 h dpp0 fe00 h 00 h cpu data page pointer 0 register (10 bits) 0000 h dpp1 fe02 h 01 h cpu data page pointer 1 register (10 bits) 0001 h dpp2 fe04 h 02 h cpu data page pointer 2 register (10 bits) 0002 h dpp3 fe06 h 03 h cpu data page pointer 3 register (10 bits) 0003 h exicon b f1c0 h e e0 h external interrupt control register 0000 h mdc b ff0e h 87 h cpu multiply divide control register 0000 h mdh fe0c h 06 h cpu multiply divide register ?high word 0000 h mdl fe0e h 07 h cpu multiply divide register ?low word 0000 h special function registers overview (cont d) name physical address 8-bit address description reset value c167cr semiconductor group 33 odp2 b f1c2 h e e1 h port 2 open drain control register 0000 h odp3 b f1c6 h e e3 h port 3 open drain control register 0000 h odp6 b f1ce h e e7 h port 6 open drain control register 00 h odp7 b f1d2 h e e9 h port 7 open drain control register 00 h odp8 b f1d6 h e eb h port 8 open drain control register 00 h ones ff1e h 8f h constant value 1? register (read only) ffff h p0l b ff00 h 80 h port 0 low register (lower half of port0) 00 h p0h b ff02 h 81 h port 0 high register (upper half of port0) 00 h p1l b ff04 h 82 h port 1 low register (lower half of port1) 00 h p1h b ff06 h 83 h port 1 high register (upper half of port1) 00 h p2 b ffc0 h e0 h port 2 register 0000 h p3 b ffc4 h e2 h port 3 register 0000 h p4 b ffc8 h e4 h port 4 register (8 bits) 00 h p5 b ffa2 h d1 h port 5 register (read only) xxxx h p6 b ffcc h e6 h port 6 register (8 bits) 00 h p7 b ffd0 h e8 h port 7 register (8 bits) 00 h p8 b ffd4 h ea h port 8 register (8 bits) 00 h pecc0 fec0 h 60 h pec channel 0 control register 0000 h pecc1 fec2 h 61 h pec channel 1 control register 0000 h pecc2 fec4 h 62 h pec channel 2 control register 0000 h pecc3 fec6 h 63 h pec channel 3 control register 0000 h pecc4 fec8 h 64 h pec channel 4 control register 0000 h pecc5 feca h 65 h pec channel 5 control register 0000 h pecc6 fecc h 66 h pec channel 6 control register 0000 h pecc7 fece h 67 h pec channel 7 control register 0000 h picon f1c4 h e e2 h port input threshold control register 0000 h pp0 f038 h e 1c h pwm module period register 0 0000 h pp1 f03a h e 1d h pwm module period register 1 0000 h pp2 f03c h e 1e h pwm module period register 2 0000 h special function registers overview (cont d) name physical address 8-bit address description reset value c167cr semiconductor group 34 pp3 f03e h e 1f h pwm module period register 3 0000 h psw b ff10 h 88 h cpu program status word 0000 h pt0 f030 h e 18 h pwm module up/down counter 0 0000 h pt1 f032 h e 19 h pwm module up/down counter 1 0000 h pt2 f034 h e 1a h pwm module up/down counter 2 0000 h pt3 f036 h e 1b h pwm module up/down counter 3 0000 h pw0 fe30 h 18 h pwm module pulse width register 0 0000 h pw1 fe32 h 19 h pwm module pulse width register 1 0000 h pw2 fe34 h 1a h pwm module pulse width register 2 0000 h pw3 fe36 h 1b h pwm module pulse width register 3 0000 h pwmcon0 b ff30 h 98 h pwm module control register 0 0000 h pwmcon1 b ff32 h 99 h pwm module control register 1 0000 h pwmic b f17e h e bf h pwm module interrupt control register 0000 h rp0h b f108 h e 84 h system startup configuration register (rd. only) xx h s0bg feb4 h 5a h serial channel 0 baud rate generator reload register 0000 h s0con b ffb0 h d8 h serial channel 0 control register 0000 h s0eic b ff70 h b8 h serial channel 0 error interrupt control register 0000 h s0rbuf feb2 h 59 h serial channel 0 receive buffer register (read only) xx h s0ric b ff6e h b7 h serial channel 0 receive interrupt control register 0000 h s0tbic b f19c h e ce h serial channel 0 transmit buffer interrupt control register 0000 h s0tbuf feb0 h 58 h serial channel 0 transmit buffer register (write only) 00 h s0tic b ff6c h b6 h serial channel 0 transmit interrupt control register 0000 h sp fe12 h 09 h cpu system stack pointer register fc00 h sscbr f0b4 h e 5a h ssc baudrate register 0000 h ssccon b ffb2 h d9 h ssc control register 0000 h special function registers overview (cont d) name physical address 8-bit address description reset value c167cr semiconductor group 35 ssceic b ff76 h bb h ssc error interrupt control register 0000 h sscrb f0b2 h e 59 h ssc receive buffer (read only) xxxx h sscric b ff74 h ba h ssc receive interrupt control register 0000 h ssctb f0b0 h e 58 h ssc transmit buffer (write only) 0000 h ssctic b ff72 h b9 h ssc transmit interrupt control register 0000 h stkov fe14 h 0a h cpu stack overflow pointer register fa00 h stkun fe16 h 0b h cpu stack underflow pointer register fc00 h syscon b ff12 h 89 h cpu system configuration register 0xx0 h 1) t0 fe50 h 28 h capcom timer 0 register 0000 h t01con b ff50 h a8 h capcom timer 0 and timer 1 control register 0000 h t0ic b ff9c h ce h capcom timer 0 interrupt control register 0000 h t0rel fe54 h 2a h capcom timer 0 reload register 0000 h t1 fe52 h 29 h capcom timer 1 register 0000 h t1ic b ff9e h cf h capcom timer 1 interrupt control register 0000 h t1rel fe56 h 2b h capcom timer 1 reload register 0000 h t2 fe40 h 20 h gpt1 timer 2 register 0000 h t2con b ff40 h a0 h gpt1 timer 2 control register 0000 h t2ic b ff60 h b0 h gpt1 timer 2 interrupt control register 0000 h t3 fe42 h 21 h gpt1 timer 3 register 0000 h t3con b ff42 h a1 h gpt1 timer 3 control register 0000 h t3ic b ff62 h b1 h gpt1 timer 3 interrupt control register 0000 h t4 fe44 h 22 h gpt1 timer 4 register 0000 h t4con b ff44 h a2 h gpt1 timer 4 control register 0000 h t4ic b ff64 h b2 h gpt1 timer 4 interrupt control register 0000 h t5 fe46 h 23 h gpt2 timer 5 register 0000 h t5con b ff46 h a3 h gpt2 timer 5 control register 0000 h t5ic b ff66 h b3 h gpt2 timer 5 interrupt control register 0000 h t6 fe48 h 24 h gpt2 timer 6 register 0000 h t6con b ff48 h a4 h gpt2 timer 6 control register 0000 h special function registers overview (cont d) name physical address 8-bit address description reset value c167cr semiconductor group 36 1) the system configuration is selected during reset. 2) bit wdtr indicates a watchdog timer triggered reset. note: the interrupt control registers xpnic are prepared to control interrupt requests from integrated x-bus peripherals. nodes, where no x-peripherals are connected, may be used to generate software controlled interrupt requests by setting the respective xpnir bit. t6ic b ff68 h b4 h gpt2 timer 6 interrupt control register 0000 h t7 f050 h e 28 h capcom timer 7 register 0000 h t78con b ff20 h 90 h capcom timer 7 and 8 control register 0000 h t7ic b f17a h e be h capcom timer 7 interrupt control register 0000 h t7rel f054 h e 2a h capcom timer 7 reload register 0000 h t8 f052 h e 29 h capcom timer 8 register 0000 h t8ic b f17c h e bf h capcom timer 8 interrupt control register 0000 h t8rel f056 h e 2b h capcom timer 8 reload register 0000 h tfr b ffac h d6 h trap flag register 0000 h wdt feae h 57 h watchdog timer register (read only) 0000 h wdtcon ffae h d7 h watchdog timer control register 000x h 2) xp0ic b f186 h e c3 h can module interrupt control register 0000 h xp1ic b f18e h e c7 h x-peripheral 1 interrupt control register 0000 h xp2ic b f196 h e cb h x-peripheral 2 interrupt control register 0000 h xp3ic b f19e h e cf h pll interrupt control register 0000 h zeros b ff1c h 8e h constant value 0? register (read only) 0000 h special function registers overview (cont d) name physical address 8-bit address description reset value c167cr semiconductor group 37 absolute maximum ratings ambient temperature under bias ( t a ): sab-c167cr-lm............................................................................................................0 to + 70 c saf-c167cr-lm .................................................................................................................. - 40 to + 85 c sak-c167cr-lm ................................................................................................................- 40 to + 125 c storage temperature ( t st )........................................................................................?65 to + 150 c voltage on v cc pins with respect to ground ( v ss ) ............................................................- 0.5 to + 6.5 v voltage on any pin with respect to ground ( v ss ) ...................................................... - 0.5 to v cc + 0.5 v input current on any pin during overload condition ........................................................- 10 to + 10 ma absolute sum of all input currents during overload condition.............................................. |100 ma| power dissipation.............................................................................................................. ....... 1.5 w note: stresses above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during overload conditions ( v in > v cc or v in < v ss ) the voltage on pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings. parameter interpretation the parameters listed in the following partly represent the characteristics of the c167cr and partly its demands on the system. to aid in interpreting the parameters right, when evaluating them for a design, they are marked in column ?ymbol? cc ( c ontroller c haracteristics): the logic of the c167cr will provide signals with the respective timing characteristics. sr ( s ystem r equirement): the external system must provide signals with the respective timing characteristics to the c167cr. c167cr semiconductor group 38 dc characteristics v cc = 5 v 10 %; v ss = 0 v; f cpu = 20 mhz; reset active t a = 0 to +70 ?c for sab-c167cr-lm t a = - 40 to + 85 ?c for saf-c167cr-lm t a = - 40 to + 125 ?c for sak-c167cr-lm parameter symbol limit values unit test condition min. max. input low voltage (ttl) v il sr ?0.5 0.2 v cc ?0.1 v input low voltage (special threshold) v ils sr ?0.5 2.0 v input high voltage, all except rstin and xtal1 (ttl) v ih sr 0.2 v cc + 0.9 v cc + 0.5 v input high voltage rstin v ih1 sr 0.6 v cc v cc + 0.5 v input high voltage xtal1 v ih2 sr 0.7 v cc v cc + 0.5 v input high voltage (special threshold) v ihs sr 0.8 v cc ? 0.2 v cc + 0.5 v input hysteresis (special threshold) hys 400 ?mv output low voltage (port0, port1, port 4, ale, rd , wr , bhe , clkout, rstout ) v ol cc 0.45 v i ol = 2.4 ma output low voltage (all other outputs) v ol1 cc 0.45 v i ol1 = 1.6 ma output high voltage (port0, port1, port 4, ale, rd , wr , bhe , clkout, rstout ) v oh cc 0.9 v cc 2.4 ? i oh = ?500 m a i oh = ?2.4 ma output high voltage 1) (all other outputs) v oh1 cc 0.9 v cc 2.4 ? v i oh = ?250 m a i oh = ?1.6 ma input leakage current (port 5) i oz1 cc 200 na 0.45v < v in < v cc input leakage current (all other) i oz2 cc 500 na 0.45v < v in < v cc overload current i ov sr 5ma 5) 8) rstin pullup resistor r rst cc 50 250 k w read/write inactive current 4) i rwh 2) 40 m a v out = 2.4 v read/write active current 4) i rwl 3) ?500 m a v out = v olmax ale inactive current 4) i alel 2) ?0 m a v out = v olmax ale active current 4) i aleh 3) 500 m a v out = 2.4 v port 6 inactive current 4) i p6h 2) 40 m a v out = 2.4 v c167cr semiconductor group 39 notes 1) this specification is not valid for outputs which are switched to open drain mode. in this case the respective output will float and the voltage results from the external circuitry. 2) the maximum current may be drawn while the respective signal line remains inactive. 3) the minimum current must be drawn in order to drive the respective signal line active. 4) this specification is only valid during reset, or during hold- or adapt-mode. port 6 pins are only affected, if they are used for cs output and the open drain function is not enabled. 5) not 100 % tested, guaranteed by design characterization. 6) the supply current is a function of the operating frequency. this dependency is illustrated in the figure below. these parameters are tested at v ccmax and 20 mhz cpu clock with all outputs disconnected and all inputs at v il or v ih . 7) this parameter is tested including leakage currents. all inputs (including pins configured as inputs) at 0 v to 0.1 v or at v cc ? 0.1 v to v cc , v ref = 0 v, all outputs (including pins configured as outputs) disconnected. 8) overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. v ov > v cc + 0.5 v or v ov < v ss 0.5v). the absolute sum of input overload currents on all port pins may not exceed 50 ma . port 6 active current 4) i p6l 3) ?500 m a v out = v ol1max port0 configuration current 4) i p0h 2) 10 m a v in = v ihmin i p0l 3) ?100 m a v in = v ilmax xtal1 input current i il cc 20 m a 0 v < v in < v cc pin capacitance 5) (digital inputs/outputs) c io cc 10 pf f = 1 mhz t a = 25 c power supply current i cc 20 + 5 f cpu ma rstin = v il2 f cpu in [mhz] 6) idle mode supply current i id 20 + 2 f cpu ma rstin = v ih1 f cpu in [mhz] 6) power-down mode supply current i pd 100 m a v cc = 5.5 v 7) parameter symbol limit values unit test condition min. max. c167cr semiconductor group 40 figure 8 supply/idle current as a function of operating frequency c167cr semiconductor group 41 a/d converter characteristics v cc = 5 v 10 %; v ss = 0 v t a = 0 to + 70 ?c for sab-c167cr-lm t a = ?40 to + 85 ?c for saf-c167cr-lm t a = ?40 to + 125 ?c for sak-c167cr-lm 4.0 v v aref v cc + 0.1 v; v ss ?0.1 v v agnd v ss + 0.2 v sample time and conversion time of the c167cr? adc are programmable. the table below should be used to calculate the above timings. parameter symbol limit values unit test condition min. max. analog input voltage range v ain sr v agnd v aref v 1) sample time t s cc ?2 t sc 2) 4) conversion time t c cc 14 t cc + t s + 4tcl 3) 4) total unadjusted error tue cc 2 lsb 5) internal resistance of reference voltage source r aref sr t cc / 165 ?0.25 k w t cc in [ns] 6) 7) internal resistance of analog source r asrc sr t s / 330 ?0.25 k w t s in [ns] 2) 7) adc input capacitance c ain cc 33 pf 7) adcon.15|14 (adctc) conversion clock t cc adcon.13|12 (adstc) sample clock t sc 00 tcl 24 00 t cc 01 reserved, do not use 01 t cc 2 10 tcl 96 10 t cc 4 11 tcl 48 11 t cc 8 c167cr semiconductor group 42 notes 1) v ain may exceed v agnd or v aref up to the absolute maximum ratings. however, the conversion result in these cases will be x000 h or x3ff h , respectively. 2) during the sample time the input capacitance c i can be charged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach its final voltage level within t s . after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t sc depend on programming and can be taken from the table above. 3) this parameter includes the sample time t s , the time for determining the digital result and the time to load the result register with the conversion result. values for the conversion clock t cc depend on programming and can be taken from the table above. 4) this parameter depends on the adc control logic. it is not a real maximum value, but rather a fixum. 5) tue is tested at v aref = 5.0 v, v agnd = 0 v, v cc = 4.9 v. it is guaranteed by design characterization for all other voltages within the defined voltage range. the specified tue is guaranteed only if an overload condition (see i ov specification) occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 ma. during the reset calibration sequence the maximum tue may be 4 lsb. 6) during the conversion the adc? capacitance must be repeatedly charged or discharged. the internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within t cc . the maximum internal resistance results from the programmed conversion timing. 7) not 100 % tested, guaranteed by design characterization. c167cr semiconductor group 43 testing waveforms figure 9 input output waveforms figure 10 float waveforms ac inputs during testing are driven at 2.4 v for a logic ??and 0.4 v for a logic ?? timing measurements are made at v ih min for a logic ??and v il max for a logic ?? for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, but begins to float when a 100 mv change from the loaded v oh / v ol level occurs ( i oh / i ol = 20 ma). c167cr semiconductor group 44 ac characteristics definition of internal timing the internal operation of the c167cr is controlled by the internal cpu clock f cpu . both edges of the cpu clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. the specification of the external timing (ac characteristics) therefore depends on the time between two consecutive edges of the cpu clock, called ?cl?(see figure below). figure 11 generation mechanisms for the cpu clock the cpu clock signal can be generated via different mechanisms. the duration of tcls and their variation (and also the derived external timing) depends on the used mechanism to generate f cpu . this influence must be regarded when calculating the timings for the c167cr. direct drive when pin p0.15 (p0h.7) is low (?? during reset the on-chip phase locked loop is disabled and the cpu clock is directly driven from the oscillator with the input clock signal. the frequency of f cpu directly follows the frequency of f xtal so the high and low time of f cpu (i.e. the duration of an individual tcl) is defined by the duty cycle of the input clock f xtal . the timings listed below that refer to tcls therefore must be calculated using the minimum tcl that is possible under the respective circumstances. this minimum value can be calculated via the following formula: tcl min = 1/ f xtal dc min (dc = duty cycle) for two consecutive tcls the deviation caused by the duty cycle of f xtal is compensated so the duration of 2tcl is always 1/ f xtal . the minimum value tcl min therefore has to be used only once for timings that require an odd number of tcls (1,3,...). timings that require an even number of tcls (2,4,...) may use the formula 2tcl = 1/ f xtal . note: the address float timings in multiplexed bus mode (t 11 and t 45 ) use the maximum duration of tcl (tcl max = 1/ f xtal dc max ) instead of tcl min . c167cr semiconductor group 45 phase locked loop when pin p0.15 (p0h.7) is high (?? during reset the on-chip phase locked loop is enabled and provides the cpu clock. the pll multiplies the input frequency by 4 (i.e. f cpu = f xtal 4). with every fourth transition of f xtal the pll circuit synchronizes the cpu clock to the input clock. this synchronization is done smoothly, i.e. the cpu clock frequency does not change abruptly. due to this adaptation to the input clock the frequency of f cpu is constantly adjusted so it is locked to f xtal . the slight variation causes a jitter of f cpu which also effects the duration of individual tcls. the timings listed in the ac characteristics that refer to tcls therefore must be calculated using the minimum tcl that is possible under the respective circumstances. the actual minimum value for tcl depends on the jitter of the pll. as the pll is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one tcl is lower than for one single tcl (see formula and figure below). for a period of n tcl the minimum value is computed using the corresponding deviation d n : tcl min = tcl nom (1 ?d n / 100) d n = (4 ? n /15) [%], where n = number of consecutive tcls and 1 n 40. so for a period of 3 tcls (i.e. n = 3): d 3 = 4 ? 3 /15 = 3.8 %, and tcl min = tcl nom (1 ?3.8 / 100) = tcl nom 0.962 (24.1 nsec @ f cpu = 20 mhz). this is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. for all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the pll jitter is neglectible. figure 12 approximated maximum pll jitter c167cr semiconductor group 46 ac characteristics external clock drive xtal1 v cc = 5 v 10 %; v ss = 0 v t a = 0 to + 70 ?c for sab-c167cr-lm t a = - 40 to + 85 ?c for saf-c167cr-lm t a = - 40 to + 125 ?c for sak-c167cr-lm 1) for temperatures above t a = + 85 ?c the minimum value for t 1 and t 2 is 25 ns. 2) the clock input signal must reach the defined levels v il and v ih2 . figure 13 external clock drive xtal1 parameter symbol direct drive 1:1 pll 1:4 unit min. max. min. max. oscillator period t osc sr 50 1000 200 333 ns high time t 1 sr 23 1) 2) ?0 ns low time t 2 sr 23 1) 2) ?0 ns rise time t 3 sr 10 2) 10 2) ns fall time t 4 sr 10 2) 10 2) ns c167cr semiconductor group 47 memory cycle variables the timing tables below use three variables which are derived from the busconx registers and represent the special characteristics of the programmed memory cycle. the following table describes, how these variables are to be computed. ac characteristics multiplexed bus v cc = 5 v 10 %; v ss = 0 v t a = 0 to + 70 ?c for sab-c167cr-lm t a = - 40 to + 85 ?c for saf-c167cr-lm t a = - 40 to + 125 ?c for sak-c167cr-lm c l (for port0, port1, port 4, ale, rd , wr , bhe , clkout) = 100 pf c l (for port 6, cs ) = 100 pf ale cycle time = 6 tcl + 2 t a + t c + t f (150 ns at 20-mhz cpu clock without waitstates) description symbol values ale extension t a tcl c167cr semiconductor group 48 rd to valid data in (with rw-delay) t 14 sr 30 + t c 2tcl ?20 + t c ns rd to valid data in (no rw-delay) t 15 sr 55 + t c 3tcl ?20 + t c ns ale low to valid data in t 16 sr 55 + t a + t c 3tcl ?20 + t a + t c ns address to valid data in t 17 sr 70 + 2 t a + t c 4tcl ?30 + 2 t a + t c ns data hold after rd rising edge t 18 sr0 0?s data float after rd t 19 sr 35 + t f 2tcl ?15 + t f ns data valid to wr t 22 sr 25 + t c 2tcl ?25 + t c ?s data hold after wr t 23 cc 35 + t f 2tcl ?15 + t f ?s ale rising edge after rd , wr t 25 cc 35 + t f 2tcl ?15 + t f ?s address hold after rd , wr t 27 cc 35 + t f 2tcl ?15 + t f ?s ale falling edge to cs t 38 cc ?5 t a 10 ? t a ?5 t a 10 t a ns cs low to valid data in t 39 sr 55 + t c + 2 t a 3tcl ?20 + t c + 2 t a ns cs hold after rd , wr t 40 cc 60 + t f 3tcl ?15 + t f ?s ale fall. edge to rdcs , wrcs (with rw delay) t 42 cc 20 + t a tcl ?5 + t a ?s ale fall. edge to rdcs , wrcs (no rw delay) t 43 cc ?5 + t a 5 + t a ?s address float after rdcs , wrcs (with rw delay) t 44 cc 0?ns address float after rdcs , wrcs (no rw delay) t 45 cc 25 tcl ns rdcs to valid data in (with rw delay) t 46 sr 25 + t c 2tcl ?25 + t c ns parameter symbol max. cpu clock = 20 mhz variable cpu clock 1/2tcl = 1 to 20 mhz unit min. max. min. max. c167cr semiconductor group 49 rdcs to valid data in (no rw delay) t 47 sr 50 + t c 3tcl ?25 + t c ns rdcs , wrcs low time (with rw delay) t 48 cc 40 + t c 2tcl ?10 + t c ?s rdcs , wrcs low time (no rw delay) t 49 cc 65 + t c 3tcl ?10 + t c ?s data valid to wrcs t 50 cc 35 + t c 2tcl ?15 + t c ?s data hold after rdcs t 51 sr0 0?s data float after rdcs t 52 sr 30 + t f 2tcl ?20 + t f ns address hold after rdcs , wrcs t 54 cc 30 + t f 2tcl ?20 + t f ?s data hold after wrcs t 56 cc 30 + t f 2tcl ?20 + t f ?s parameter symbol max. cpu clock = 20 mhz variable cpu clock 1/2tcl = 1 to 20 mhz unit min. max. min. max. c167cr semiconductor group 50 figure 14-1 external memory cycle: multiplexed bus, with read/write delay, normal ale data in data out address address t 38 t 44 t 10 address ale csx a23-a16 (a15-a8) bhe bus read cycle rd rdcsx bus write cycle wr , wrl , wrh wrcsx t 5 t 16 t 17 t 6 t 7 t 39 t 40 t 25 t 27 t 18 t 19 t 14 t 46 t 12 t 48 t 10 t 22 t 23 t 44 t 12 t 48 t 8 t 42 t 42 t 8 t 50 t 51 t 54 t 52 t 56 c167cr semiconductor group 51 figure 14-2 external memory cycle: multiplexed bus, with read/write delay, extended ale data out address data in address t 38 t 44 t 10 address ale csx a23-a16 (a15-a8) bhe bus read cycle rd rdcsx bus write cycle wr , wrl , wrh wrcsx t 5 t 16 t 17 t 6 t 7 t 39 t 40 t 25 t 27 t 18 t 19 t 14 t 46 t 12 t 48 t 10 t 22 t 23 t 44 t 12 t 48 t 8 t 42 t 42 t 8 t 50 t 51 t 54 t 52 t 56 c167cr semiconductor group 52 figure 14-3 external memory cycle: multiplexed bus, no read/write delay, normal ale data out address address data in t 38 address ale csx a23-a16 (a15-a8) bhe bus read cycle rd rdcsx bus write cycle wr , wrl , wrh wrcsx t 5 t 16 t 17 t 6 t 7 t 39 t 40 t 25 t 27 t 18 t 19 t 15 t 47 t 13 t 49 t 22 t 23 t 13 t 49 t 9 t 43 t 43 t 9 t 11 t 45 t 11 t 45 t 50 t 51 t 54 t 52 t 56 c167cr semiconductor group 53 figure 14-4 external memory cycle: multiplexed bus, no read/write delay, extended ale data out address data in address t 38 address ale csx a23-a16 (a15-a8) bhe bus read cycle rd rdcsx bus write cycle wr , wrl , wrh wrcsx t 5 t 16 t 17 t 6 t 7 t 39 t 40 t 25 t 27 t 18 t 19 t 15 t 47 t 13 t 49 t 22 t 23 t 13 t 49 t 9 t 43 t 43 t 9 t 11 t 45 t 11 t 45 t 50 t 51 t 54 t 52 t 56 c167cr semiconductor group 54 ac characteristics demultiplexed bus v cc = 5 v 10 %; v ss = 0 v t a = 0 to + 70 ?c for sab-c167cr-lm t a = - 40 to + 85 ?c for saf-c167cr-lm t a = - 40 to + 125 ?c for sak-c167cr-lm c l (for port0, port1, port 4, ale, rd , wr , bhe , clkout) = 100 pf c l (for port 6, cs ) = 100 pf ale cycle time = 4 tcl + 2 t a + t c + t f (100 ns at 20-mhz cpu clock without waitstates) parameter symbol max. cpu clock = 20 mhz variable cpu clock 1/2tcl = 1 to 20 mhz unit min. max. min. max. ale high time t 5 cc 15 + t a tcl ?10 + t a ?s address setup to ale t 6 cc 10 + t a tcl ?15 + t a ?s ale falling edge to rd , wr (with rw-delay) t 8 cc 15 + t a tcl ?10 + t a ?s ale falling edge to rd , wr (no rw-delay) t 9 cc ?10 + t a 10 + t a ?s rd , wr low time (with rw-delay) t 12 cc 40 + t c 2tcl ?10 + t c ?s rd , wr low time (no rw-delay) t 13 cc 65 + t c 3tcl ?10 + t c ?s rd to valid data in (with rw-delay) t 14 sr 30 + t c 2tcl ?20 + t c ns rd to valid data in (no rw-delay) t 15 sr 55 + t c 3tcl ?20 + t c ns ale low to valid data in t 16 sr 55 + t a + t c 3tcl ?20 + t a + t c ns address to valid data in t 17 sr 70 + 2 t a + t c 4tcl ?30 + 2 t a + t c ns data hold after rd rising edge t 18 sr0 0?s data float after rd rising edge (with rw-delay 1) ) t 20 sr 35 + t f 2tcl ?15 + 2 t a + t f 1) ns data float after rd rising edge (no rw-delay 1) ) t 21 sr 15 + t f tcl ?10 + 2 t a + t f 1) ns data valid to wr t 22 cc 25 + t c 2tcl ?25 + t c ?s data hold after wr t 24 cc 15 + t f tcl ?10 + t f ?s c167cr semiconductor group 55 1) rw-delay and t a refer to the next following bus cycle. ale rising edge after rd , wr t 26 cc ?10 + t f 10 + t f ?s address hold after rd , wr t 28 cc 0 + t f ? + t f ?s ale falling edge to cs t 38 cc ?5 t a 10 t a ? t a 10 t a ns cs low to valid data in t 39 sr 55 + t c + 2 t a 3tcl ?20 + t c + 2 t a ns cs hold after rd , wr t 41 cc 10 + t f tcl ?15 + t f ?s ale falling edge to rdcs , wrcs (with rw- delay) t 42 cc 20 + t a tcl ?5 + t a ?s ale falling edge to rdcs , wrcs (no rw- delay) t 43 cc ?5 + t a 5 + t a ?s rdcs to valid data in (with rw-delay) t 46 sr 25 + t c 2tcl ?25 + t c ns rdcs to valid data in (no rw-delay) t 47 sr 50 + t c 3tcl ?25 + t c ns rdcs , wrcs low time (with rw-delay) t 48 cc 40 + t c 2tcl ?10 + t c ?s rdcs , wrcs low time (no rw-delay) t 49 cc 65 + t c 3tcl ?10 + t c ?s data valid to wrcs t 50 cc 35 + t c 2tcl ?15 + t c ?s data hold after rdcs t 51 sr0 0?s data float after rdcs (with rw-delay) t 53 sr 30 + t f 2tcl ?20 + t f ns data float after rdcs (no rw-delay) t 68 sr 5 + t f tcl ?20 + t f ns address hold after rdcs , wrcs t 55 cc ?10 + t f 10 + t f ?s data hold after wrcs t 57 cc 10 + t f tcl ?15 + t f ?s parameter symbol max. cpu clock = 20 mhz variable cpu clock 1/2tcl = 1 to 20 mhz unit min. max. min. max. c167cr semiconductor group 56 figure 15-1 external memory cycle: demultiplexed bus, with read/write delay, normal ale data out data in t 38 address ale csx a23-a16 a15-a0 bhe bus (d15-d8) d7-d0 read cycle rd rdcsx write cycle wrcsx t 5 t 16 t 17 t 6 t 39 t 41 t 26 t 28 t 18 t 20 t 14 t 46 t 12 t 48 t 22 t 24 t 12 t 48 t 8 t 42 t 42 t 8 t 50 t 51 t 55 t 53 t 57 bus (d15-d8) d7-d0 wr , wrl , wrh c167cr semiconductor group 57 figure 15-2 external memory cycle: demultiplexed bus, with read/write delay, extended ale data out data in t 38 address ale csx a23-a16 a15-a0 bhe read cycle rd rdcsx write cycle wrcsx t 5 t 16 t 17 t 6 t 39 t 41 t 26 t 28 t 18 t 20 t 14 t 46 t 12 t 48 t 22 t 24 t 12 t 48 t 8 t 42 t 42 t 8 t 50 t 51 t 55 t 53 t 57 bus (d15-d8) d7-d0 bus (d15-d8) d7-d0 wr , wrl , wrh c167cr semiconductor group 58 figure 15-3 external memory cycle: demultiplexed bus, no read/write delay, normal ale data out data in t 38 address ale csx a23-a16 a15-a0 bhe read cycle rd rdcsx write cycle wrcsx t 5 t 16 t 17 t 6 t 39 t 41 t 26 t 28 t 18 t 21 t 15 t 47 t 13 t 49 t 22 t 24 t 13 t 49 t 9 t 43 t 43 t 9 t 50 t 51 t 55 t 68 t 57 bus (d15-d8) d7-d0 bus (d15-d8) d7-d0 wr , wrl , wrh c167cr semiconductor group 59 figure 15-4 external memory cycle: demultiplexed bus, no read/write delay, extended ale data out data in t 38 address ale csx a23-a16 a15-a0 bhe read cycle rd rdcsx write cycle wr , wrl , wrh wrcsx t 5 t 16 t 17 t 6 t 39 t 41 t 26 t 28 t 18 t 21 t 15 t 47 t 13 t 49 t 22 t 24 t 13 t 49 t 9 t 43 t 43 t 9 t 50 t 51 t 55 t 68 t 57 bus (d15-d8) d7-d0 bus (d15-d8) d7-d0 c167cr semiconductor group 60 ac characteristics clkout and ready v cc = 5 v 10 %; v ss = 0 v t a = 0 to +70 ?c for sab-c167cr-lm t a = -40 to +85 ?c for saf-c167cr-lm t a = -40 to +125 ?c for sak-c167cr-lm c l (for port0, port1, port 4, ale, rd , wr , bhe , clkout) = 100 pf c l (for port 6, cs ) = 100 pf notes 1) these timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2) demultiplexed bus is the worst case. for multiplexed bus 2tcl are to be added to the maximum values. this adds even more time for deactivating ready . the 2t a refer to the next following bus cycle. parameter symbol max. cpu clock = 20 mhz variable cpu clock 1/2tcl = 1 to 20 mhz unit min. max. min. max. clkout cycle time t 29 cc 50 50 2tcl 2tcl ns clkout high time t 30 cc 20 tcl ?5 ns clkout low time t 31 cc 15 tcl ?10 ns clkout rise time t 32 cc 5?ns clkout fall time t 33 cc 5?ns clkout rising edge to ale falling edge t 34 cc 0 + t a 10 + t a 0 + t a 10 + t a ns synchronous ready setup time to clkout t 35 sr 15 15 ns synchronous ready hold time after clkout t 36 sr0 0?s asynchronous ready low time t 37 sr 65 2tcl + 15 ns asynchronous ready setup time 1) t 58 sr 15 15 ns asynchronous ready hold time 1) t 59 sr 0 0?s async. ready hold time after rd , wr high (demultiplexed bus) 2) t 60 sr 00 + 2 t a + t f 2) 0 tcl - 25 + 2 t a + t f 2) ns c167cr semiconductor group 61 figure 16 clkout and ready notes 1) cycle as programmed, including mctc waitstates (example shows 0 mctc ws). 2) the leading edge of the respective command depends on rw-delay. 3) ready sampled high at this sampling point generates a ready controlled waitstate, ready sampled low at this sampling point terminates the currently running bus cycle. 4) ready may be deactivated in response to the trailing (rising) edge of the corresponding command (rd or wr ). 5) if the asynchronous ready signal does not fulfill the indicated setup and hold times with respect to clkout (e.g. because clkout is not enabled), it must fulfill t 37 in order to be safely synchronized. this is guaranteed, if ready is removed in response to the command (see note 4) ). 6) multiplexed bus modes have a mux waitstate added after a bus cycle, and an additional mttc waitstate may be inserted here. for a multiplexed bus with mttc waitstate this delay is 2 clkout cycles, for a demultiplexed bus without mttc waitstate this delay is zero. 7) the next external bus cycle may start here. clkout ale t 30 t 34 sync ready t 35 t 36 t 35 t 36 async ready t 58 t 59 t 58 t 59 waitstate ready mux/tristate 6) t 32 t 33 t 29 running cycle 1) t 31 t 37 3) 3) 5) command rd , wr t 60 4) see 6) 2) 7) 3) 3) c167cr semiconductor group 62 ac characteristics external bus arbitration v cc = 5 v 10 %; v ss = 0 v t a = 0 to + 70 ?c for sab-c167cr-lm t a = ?40 to + 85 ?c for saf-c167cr-lm t a = ?40 to + 125 ?c for sak-c167cr-lm c l (for port0, port1, port 4, ale, rd , wr , bhe , clkout) = 100 pf c l (for port 6, cs ) = 100 pf parameter symbol max. cpu clock = 20 mhz variable cpu clock 1/2tcl = 1 to 20 mhz unit min. max. min. max. hold input setup time to clkout t 61 sr 20 20 ns clkout to hlda high or breq low delay t 62 cc 20 20 ns clkout to hlda low or breq high delay t 63 cc 20 20 ns csx release t 64 cc 20 20 ns csx drive t 65 cc ?5 25 5 25 ns other signals release t 66 cc 20 20 ns other signals drive t 67 cc ?5 25 5 25 ns c167cr semiconductor group 63 figure 17 external bus arbitration, releasing the bus notes 1) the c167cr will complete the currently running bus cycle before granting bus access. 2) this is the first possibility for breq to get active. 3) the cs outputs will be resistive high (pullup) after t 64 . clkout hold t 61 hlda t 63 other signals t 66 1) csx (on p6.x) t 64 1) 2) breq t 62 3) c167cr semiconductor group 64 figure 18 external bus arbitration, (regaining the bus) notes 1) this is the last chance for breq to trigger the indicated regain-sequence. even if breq is activated earlier, the regain-sequence is initiated by hold going high. please note that hold may also be deactivated without the c167cr requesting the bus. 2) the next c167cr driven bus cycle may start here. clkout hold hlda other signals t 62 csx (on p6.x) t 67 t 62 1) 2) t 65 t 61 breq t 63 t 62 |
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